1. Field of the Invention
The present invention relates to an apparatus and method for controlling CPU speed transition, and more particularly to a CPU speed transition.
2. Background of the Related Art
FIG. 1 is a flow chart illustrating a related art CPU speed transition control method applied to a computer system. For example, if an SMI (System Management Interrupt) signal occurs in a notebook computer at step S10, a system BIOS of the notebook computer recognizes why the SMI signal has occurred at step S11.
Unless the reason for the SMI signal occurrence is to perform a transition of Geyserville CPU speed at step S12, the system BIOS processes a prescribed operation corresponding to the SMI signal at step S13. Otherwise, if the SMI signal has occurred to perform Geyserville CPU speed transition either from high speed to low speed or from low speed to high speed, it is determined whether a bus master device in the notebook computer is in an active state at step S14.
If the bus master device is not in the active state, the system BIOS sets a transition flag to a first prescribed value indicative of transition success at step S15, and increases or decreases the Geyserville CPU speed at step S16.
The system BIOS determines whether the Geyserville CPU speed transition is normally executed at step S17. In this case, if the Geyserville CPU speed transition is abnormally executed, the system BIOS sets a transition flag to a second prescribed value indicative of transition failure at step S18, and terminates the SMI service operation at step S19.
If it is determined that the bus master device is in the active state at step S14, the system BIOS sets the transition flag to the second prescribed value indicative of transition failure without performing the Geyserville CPU speed transition at step S18. Then, the system BIOS terminates the SMI service operation at step S19 so that it can prevent a computer system from hanging up. Thereafter, the system BIOS repeats the above-described steps until receiving a system-off command at step S20.
The reason why the computer system hangs up is as follows. When the system BIOS performs CPU speed transition when the bus master device (from among several system devices) is in an active state, the CPU is not in a normal mode while performing the CPU speed transition, and the system BIOS cannot continuously perform the bus master device's current operations any longer. Accordingly, the computer system hang up is avoided by preventing the CPU speed transition when the bus master device is active.
As described above, the related art apparatus and method for controlling CPU speed transition have various disadvantages. For example, if the bus master device is in the active state and the system BIOS immediately terminates the SMI service without performing the CPU speed transition, the computer system does not hang up, however, the SMI service is terminated because of transition failure. Therefore, it is difficult or impossible for the system BIOS to normally perform the CPU speed transition.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.